Zarlink Semiconductor (TSX: ZL) and Vitesse Semiconductor Corporation (NASDAQ: VTSS) today announced availability of a joint reference design that delivers synchronization required by carriers to deliver scalable, higher bandwidth communication services over packet-based networks. Using technology based on Zarlink\'s Synchronous Ethernet system synchronizer and Vitesse\'s Carrier Ethernet Gigabit PHY, the reference design speeds development time of next-generation network products, enabling customers to leverage Vitesse and Zarlink synchronization and timing expertise and shorten time-to-market.

The explosive bandwidth demand driven by mobile data and video applications has prompted upgrade of legacy Time Division Multiplexing (TDM) based basestation, backhaul, and access platforms to lower-cost packet-based networks. Unlike TDM networks, packet-based networks do not inherently carry clock synchronization information. Therefore, precision timing synchronization is critical for service providers, in order to support higher bandwidth time-critical services in wireless backhaul, business services and smart grid applications in the newer networks.

\"Packet-based Ethernet technologies enable carriers to cost-effectively scale bandwidth to meet the demands of new mobile multimedia applications,\" said Jamileh Davoudi, product marketing manager with Zarlink\'s Timing and Synchronization product line. \"Zarlink and Vitesse have combined our Synchronous Ethernet timing expertise to provide manufacturers with an easy-to-implement solution to support multiple services over a single network. In addition, this reference design allows the flexibility to upgrade designs to IEEE 1588v2 for wireless technologies, such as WCDMA-TDD, CDMA2000 and Mobile WiMAX.\"

The reference design combines Zarlink\'s ZL30143 Synchronous Ethernet (SyncE) dual channel system synchronizer and Vitesse\'s VSC8574 Gigabit PHY transceiver. The Vitesse PHY provides both primary and secondary recovered clock outputs as clock references to Zarlink\'s ZL30143 in the synchronous timing system to provide a low jitter Synchronous Ethernet solution. The reference design meets the performance demands for timing synchronization in accordance with ITU-T Recommendation G.8262 for wireless base stations, radio network controllers, gateways, aggregation and transmission equipment, and routers while reducing design complexity. For applications requiring IEEE 1588v2 phase and time synchronization, Vitesse\'s VSC8574 device provides both one-step and two-step time stamping in the physical layer with +/-10ns or better accuracy and can be complemented with Zarlink\'s ZL3034x family of IEEE 1588v2-enabled timing products. 

\"Our reference design with Zarlink gives equipment manufacturers and service providers a seamless upgrade path to integrate precise timing features required to deliver advanced communication services over lower-cost packet networks,\" said Brian Jaroszewski, senior product manager at Vitesse. \"Complemented by our broad Carrier Ethernet portfolio of GE, 10GE and OTN PHY devices with IEEE 1588v2 support, Vitesse offers full network synchronization support sufficient for WiMAX and LTE backhaul, as well as other timing critical applications.\"

More information please visit http://www.zarlink.com/zarlink/hs/press_releases_23611.htm or contact Mr. Jacky Su at Seraphim,Taiwan distributor of Zarlink, tel: 26984660 ext. 216 or email to jackysu@seraphim.com.tw

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